IP Core Design Engineer

Intel

Gdansk, PL

3 d. temu

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Infrastructure And Platform Solutions Group (IPSG) as an IP Design Engineer!As an IP Design Engineer you will design models for Image / Vision processing and Neural Networks components of complex IP logic.

You will develop verify and validate IP core models using MATLAB / Simulink and System Verilog DPI Components and / or C / C++ and / or System Verilog / RTL.

Your work will directly contribute to the design and health of Intel architecture based next generation SoC products.Additional responsibilities will include, but not be limited to : - Collaborate with Architecture team and Verification team to deliver functionally correct golden models.

Support silicon validation and silicon debug- Thoroughly understand design specs to develop golden model / executable specification- Be able to think through design corner cases and be able to write relevant cover points

Qualifications

Important for us : - Ability to work in a dynamic and team oriented environment- Problem-solving skills, including debugging and brainstorming techniques- Strong written and verbal communication skills- In this position, you will gain invaluable experience, which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

IP logic design and verification using RTL- 7+ years of experience in logic design and / or verification using Verilog / System Verilog- 7+ years of experience developing verification collateral in Verilog, System Verilog and UVM- Prior work experience with complex coverage driven random constraint UVM environments (UVM fluency is a must)- Able to put together complex UVM environments from scratchBig advantage for us would be : - Artificial Intelligence / Deep Learning / Machine Learning experience- Image and Vision processing experience- Experience in complex high-speed FSMs design- Experience and understanding of Static Timing Analysis (STA)- Technical leadership experience- 7+ years of experience and knowledge of computer architecture / micro-architecture.

Ability to take design from concept to microarchitecture Bachelor's / Master's degree / PhD in Electrical Engineering, Computer Engineering with industry experienceA fluent in Polish and English in both verbal and written forms.

Additional Qualifications : - RTL logic design and verification- Deep knowledge in chosen areas : Simulation tools like Synopsys : VCS, VCSMX, VERDI System Verilog (Verilog) language RTL coding for ASIC synthesis reusing component libraries (DesignWare, etc.

Unit testing (UVM, or equiv.) Linting (SpyGlass, or equiv.) Formal Verification (JasperGold, VC Formal, or equiv.) Emulation / Prototyping platform (Emulation-servers / FPGA-HAPS or equiv.

ASIC Synthesis (Design Compiler or equiv.) ASIC Place & Route (IC Compiler, or equiv.)

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