Duringthe current global health crisis, the priority for Siemens Digital IndustriesSoftware is the health and wellbeing of our entire community including currentand future employees, which may add time to our hiring processes.
Weappreciate your patience and invite you to visit our website to learnmore about how Siemens is responding to the pandemic.
Mentor, aSiemens Business is looking for a highly motivated design engineer to join theR&D team developing Design-forTest tools as part of the Tessent productline.
The candidate would join the leading-edge team responsible for thedevelopment of the IEEE1149.10 product where highspeed SERDES lanes are used tocarry test data in and out of the chip.
The responsibility involves :
the designand implementation of the Verilog RTL IP with complete flow automation withinthe chip design process
integration between IEEE1149.10 with the ATPG andIJTAG components of the Tessent Shell platform is important aspect of the job
several programing languages including Verilog, TCL, C++ and several designautomation tools proprietary languages are used
Thesuccessful candidates must possess the following combination of education andexperience :
BS / MS / Ph.D.in Computer Science, Electrical or Computer Engineering, or other relatedfield.
1+ years(including one year in commercial environment) of software engineeringexperience in C++.
Workingknowledge of Linux and one or more scripting languages.
Knowledgeof digital logic design along with hardware description languages, such asVerilog or VHDL.
Stronganalysis, design, and problem-solving skills.
Attentionto details and the ability to accurately estimate software and hardware tasksand delivery on schedule.
Good verbal,written, and interpersonal communication skills in English
Goodbackground of DFT and best-known industry practices.
Knowledgeand experience in all aspects of design flows such as test, synthesis, simulation,formal verification, timing optimization, and other related design tasks.