Job Description :
The IPG IP Engineering Group located in Katowice, Poland is looking for energetic and passionate pre-Silicon Verification Engineers to verify Ultra Low Power, state of the art Neural Network Accelerator and / or soft IP cores for Intel's next generation chips / and SoC's for the different market segments.
Job role involves defining and implementing verification methodology, TB architecture, validation tests and environment to verify the IP.
Candidates need to have extensive experience in defining test plan, implementing TB components, coding sequences, checkers, assertions, coverage, and debugging RTL / GLS tests etc.
Candidates should possess extensive knowledge of System Verilog, SVA, OVM and / or UVM methodology, and driving Code and Functional coverage closure.
Knowledge of C, DPI-C, Formal Verification techniques, AMBA bus protocols is a plus. Candidates should have the ability to work effectively with both internal and external teams and stakeholders.
Strong problem solving and communication skills are desired.
Candidate should possess a Master's and / or a PhD's degree in Electronics or Electrical engineering or Computer Science engineering.
5..7 years of ASIC Front-end simulation verification for IP or SoC (System on Chip). Good understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and / or debug flows.
Experience with IO protocols like AMBA-AXI / AHB / APB, OCP. Experience on CPU, DSP and power management , upf-VCS NLP is preferred.
Extensive knowledge of System Verilog and working knowledge of verification methodologies like OVM and UVM. Good knowledge on functional and code coverage Adept in programming and / or scripting (C++, Perl and others) and be conversant with flows and tools for VLSI logic design and / or functional verification.
Good written and verbal communication skills in English and Polish language.
As an advantage :
System level emulation-based verification, emulation with ZeBu or HAPS, SLE environment. Experience with Synopsys tools.
PCIe protocol knowledge. Familiarity with ML / DL Neural Networks technology. Post-Si Validation and debug support, Assembly, System Verilog.
Intel CPU architecture or x86 architecture in general.
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process.
IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving.
We are a fearless organization transforming IP development.