System Validation Engineer
1 d. temu

Job Description

Our team needs you We are part of the Silicon Engineering organization within the Connectivity group under DPG and we are looking for an individual with proven technical leadership experience to help build our System Validation team We are a strong vibrant crosssite team who define create and develop the environment and test suites that we use to validate Ethernet products like NIC at the IP and Full chip level and working on cutting edge of compute and networking using latest Custom CoresBus architectures As part of this team you will help build a team that will work collaboratively with our peer SV teams RTL hardware design verification software engineers and platform teams to define and implement requirements for emulation prototyping and post silicon validation throughout the product life cycle You will be embedded within the mentioned teams to work in collaboration towards common test strategies and execution of those plansWe need your skills and talent in system validation to apply smart debug techniques to characterize Full Chip functional flows and issues as well as test feature correctnessperformance to specifications and use cases validation both in the presilicon and postsilicon space for Ethernet SOCIP Areas such as Inter IP Full Chip validation verifying Ethernet network and virtualization Power Management Debug DFX Clocking Reset interrupts and Security As a successful system validation technical lead or engineer on our team you will be responsible for developing the methodologies we use executing validation test plans and debugging failures that we find in Full Chip and ethernet IPs or products We will need you to have a broad understanding of multiple areas of computer architecture and system design technical test content development and you will be required to interface with our peers in SW Architecture Silicon Design and Presilicon Verification We will also need you to continue to improve our test content and provide feedback for the design and evolution of our future ondie debug and validation featuresCreates defines and develops system validation environment and test suites Uses and applies emulation and platformlevel tools and techniques to ensure performance to spec Responsible for the development of methodologies execution of validation plans and debug of failures Requires broad understanding of multiple system areas and requires interfaces with Architecture Design and Presilicon Validation teams in improving postsilicon test content and providing feedback for future ondie debug features


Required Qualifications Masters degree in Electrical Engineering Computer Engineering or Computer Science with at least 8+ years of relevant industry experience Solid understanding of PCIe protocol and the validation of PCIe interfaces or any high speed IO understanding of ethernet is an added advantage Hardware and or software development debugging skills Understanding of XML Extensible Markup Language Direct Post Silicon validation experience Experience with clocking resets Experience with DFX JTAG Array freeze and dump Experience with lab equipment Logic Analyzer Oscilloscope thermal streams protocol analyzers Experience with C Perl and or Python Experience in developing test plans Preferred Experience Object Oriented programming skills Experience developing test automation

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