Digital Verification (SnR)
Gdansk, POLAND
1 d. temu

Job Description

and Requirements At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars.

Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything.

And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.

All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.

And get differentiated products to market quickly with reduced risk. Synopsys is committed to fostering an environment that treats people with respect, honesty, and professionalism.

We’re also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.

Come and be part of a collaborative team environment that innovates .

Digital Verification (SnR)

Digital Verification Engineer, Senior is a Senior R&D Engineer whose mandate is to participate in the RTL verification of digital and / or mixed-signal logic blocks.

The successful candidate will be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation USB / PCIe / DPHY / CDPHY / MPHY / DP / HDMI products (up to 13.5 / 25Gbps).

The position offers an excellent opportunity to join an expert team of engineers. The team is responsible for delivering high-end mixed-signal products.

The PHY development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments.

The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charted unknown waters.

The team lives by the mantras :

There are no secrets for success. It is the result of preparation, hard work, and learning from failure"

  • Stop being a follower, become a leader
  • Main duties :

  • Actively support the creation of a verification team.
  • Train and support young team members
  • Participate in complex block and / or chip planning and architecture studies
  • Participate in the development of verification environments using top of the edge methodologies : System Verilog and UVM
  • Perform RTL and gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied
  • Work toward improving efficiency in design procedures and methodologies
  • Documentation of design and verification environments / plans and overall procedures
  • Development opportunities :

  • Become brave in the face of the unknown
  • Develop systematic ways to address new problems, think outside of the box
  • Produce high quality work and products
  • Have an impact on the new product architectures, quality and development strategies
  • Write patents for any inventions
  • Minimum Requirements :

  • Typically requires a minimum of 5+ years of related experience
  • Deep Understanding of IC design flows
  • Experience in Verilog / VHDL, System Verilog or VMM or OVM or UVM would be advantageous
  • Willingness to learn
  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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