ASIC/Layout Design Engr, II
Synopsys, Inc
POLAND - Gdansk, POLAND - Poland, PORTUGAL - Lisbon, PORTUGAL - Portugal
6 d. temu

Job Description and Requirements

You will be part of a layout team developing physical layout of high speed analog integrated circuits. As mixed-signal layout engineer you will be exposed to SerDes PHY layout.

As a designer of IP layout, circuits will be constructed so as to facilitate porting to multiple process nodes. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-

house tools supported by an experienced software / CAD team.

Requirements

  • In depth familiarity with layout of analog and mixed signal CMOS circuits
  • Exposure to SERDES subcircuit layout (i.e. RX, TX, PLL, etc )
  • Design for porting (i.e. design so as to enable ease moving layout across multiple foundry nodes)
  • Knowledge of signal integrity issues (i.e. clock / data routes, differential routing, shielding)
  • Aware of layout techniques to mitigate ESD, latchup
  • Familiarity with custom digital layout (i.e. high speed logic paths)
  • Knowledge of design for reliability (i.e. EM, IR, etc )
  • Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc )
  • Layout tool : Custom Designer (similar to Cadence)
  • Verification tools : ICV, Star-RCXT
  • Experience

    2+ years of relevant experience and BS / MS in Electrical Engineering or Computer Science.

    Applies company policies and procedures to resolve routine issues. Follows standard practices and specific, outlined, and detailed procedures in analyzing situations or data from which answers can be readily obtained.

    Normally receives detailed instructions on work, which is reviewed regularly by manager or more senior peers. Builds routine working relationships internally.

    Contacts are primarily with direct manager and other peers in the group or department.

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